1. Field of the Invention
The present invention relates to a memory module and memory-assist module connectable to a computer body.
2. Description of the Prior Art
Conventionally, memory expansion has been implemented by connecting memory modules to sockets (slots) of a computer body. As the memory modules, a 128-megabyte DIMM (Dual Inline Memory Module) having eight 128-megabit SDRAMs (Synchronous Dynamic Random Access Memories), a 128-megabyte DIMM (Dual Inline Memory Module) having sixteen 256-megabit SDRAMs (Synchronous Dynamic Random Access Memories), and the like are used. Generally, twelve address signal terminals A0 to A11 are provided to the 128-megabit SDRAM, to which twelve signal lines of a row address and ten signal lines of a column address can be connected. When address signals A0 to A11 are inputted from the computer body, data of an address corresponding to the address signals can be read/written from/on the whole 128-megabit areas of all the SDRAMs.
The 256-megabyte DIMM is divided into two groups (banks) of the SDRAMS. In addition to the address signals A0 to A11, a plurality of chip select signals corresponding to the banks to be accessed are inputted, so that data of the corresponding bank and address can be read/written from/on the whole of 256-megabyte area of the DIMM. As just described, by using a plurality of the chip select signals for selecting the banks, a memory capacity available for the computer body can be expanded.
A module where memories to be accessed are switched according to a state of the most significant address signal inputted from a computer body, a technique of which module is disclosed in the gazette of Japanese Patent No.3022255 (paragraphs 0014 to 0054, FIGS. 1 to 8), is also known.
In the above-described technique, there was the following problem.
Recently, 256-megabyte DIMMs each having eight 256-megabit SDRAMs have been used. However, to access the whole memory area of the 256-megabit SDRAM, row address signals A0 to A12 need to be inputted into the SDRAM. As a result, such old computer bodies that output only address signals A0 to A11 could use only the area of 128 megabits, which was half of the 256-megabit SDRAM. Also with the module of Japanese Patent No.3022255, memories to be accessed are only switched according to the most significant address signal A11, so that this module had the same problem.